// Peripheral: FLASH_Periph  FLASH Registers.
// Instances:
//  FLASH  mmap.FLASH_R_BASE
// Registers:
//  0x00 32  ACR     Access control register.
//  0x04 32  PECR    Program/erase control register.
//  0x08 32  PDKEYR  Power down key register.
//  0x0C 32  PEKEYR  Program/erase key register.
//  0x10 32  PRGKEYR Program memory key register.
//  0x14 32  OPTKEYR Option byte key register.
//  0x18 32  SR      Status register.
//  0x1C 32  OBR     Option byte register.
//  0x20 32  WRPR    Write protection register.
//  0x80 32  WRPR1   Write protection register 1.
//  0x84 32  WRPR2   Write protection register 2.
//  0x88 32  WRPR3   Write protection register 3.
// Import:
//  stm32/o/l1xx_md/mmap
package flash

// DO NOT EDIT THIS FILE. GENERATED BY stm32xgen.

const (
	LATENCY  ACR = 0x01 << 0 //+ Latency.
	PRFTEN   ACR = 0x01 << 1 //+ Prefetch Buffer Enable.
	ACC64    ACR = 0x01 << 2 //+ Access 64 bits.
	SLEEP_PD ACR = 0x01 << 3 //+ Flash mode during sleep mode.
	RUN_PD   ACR = 0x01 << 4 //+ Flash mode during RUN mode.
)

const (
	LATENCYn  = 0
	PRFTENn   = 1
	ACC64n    = 2
	SLEEP_PDn = 3
	RUN_PDn   = 4
)

const (
	PELOCK     PECR = 0x01 << 0  //+ FLASH_PECR and Flash data Lock.
	PRGLOCK    PECR = 0x01 << 1  //+ Program matrix Lock.
	OPTLOCK    PECR = 0x01 << 2  //+ Option byte matrix Lock.
	PROG       PECR = 0x01 << 3  //+ Program matrix selection.
	DATA       PECR = 0x01 << 4  //+ Data matrix selection.
	FTDW       PECR = 0x01 << 8  //+ Fixed Time Data write for Word/Half Word/Byte programming.
	ERASE      PECR = 0x01 << 9  //+ Page erasing mode.
	FPRG       PECR = 0x01 << 10 //+ Fast Page/Half Page programming mode.
	PARALLBANK PECR = 0x01 << 15 //+ Parallel Bank mode.
	EOPIE      PECR = 0x01 << 16 //+ End of programming interrupt.
	ERRIE      PECR = 0x01 << 17 //+ Error interrupt.
	OBL_LAUNCH PECR = 0x01 << 18 //+ Launch the option byte loading.
)

const (
	PELOCKn     = 0
	PRGLOCKn    = 1
	OPTLOCKn    = 2
	PROGn       = 3
	DATAn       = 4
	FTDWn       = 8
	ERASEn      = 9
	FPRGn       = 10
	PARALLBANKn = 15
	EOPIEn      = 16
	ERRIEn      = 17
	OBL_LAUNCHn = 18
)

const (
	BSY        SR = 0x01 << 0  //+ Busy.
	EOP        SR = 0x01 << 1  //+ End Of Programming.
	ENHV       SR = 0x01 << 2  //+ End of high voltage.
	READY      SR = 0x01 << 3  //+ Flash ready after low power mode.
	WRPERR     SR = 0x01 << 8  //+ Write protected error.
	PGAERR     SR = 0x01 << 9  //+ Programming Alignment Error.
	SIZERR     SR = 0x01 << 10 //+ Size error.
	OPTVERR    SR = 0x01 << 11 //+ Option validity error.
	OPTVERRUSR SR = 0x01 << 12 //+ Option User validity error.
	RDERR      SR = 0x01 << 13 //+ Read protected error.
)

const (
	BSYn        = 0
	EOPn        = 1
	ENHVn       = 2
	READYn      = 3
	WRPERRn     = 8
	PGAERRn     = 9
	SIZERRn     = 10
	OPTVERRn    = 11
	OPTVERRUSRn = 12
	RDERRn      = 13
)

const (
	RDPRT      OBR = 0x55 << 1  //+ Read Protection.
	SPRMOD     OBR = 0x01 << 8  //+ Selection of protection mode of WPRi bits.
	BOR_LEV    OBR = 0x0F << 16 //+ BOR_LEV[3:0] Brown Out Reset Threshold Level.
	IWDG_SW    OBR = 0x01 << 20 //+ IWDG_SW.
	nRST_STOP  OBR = 0x01 << 21 //+ nRST_STOP.
	nRST_STDBY OBR = 0x01 << 22 //+ nRST_STDBY.
	BFB2       OBR = 0x01 << 23 //+ BFB2(available only in STM32L1xx High-density devices).
)

const (
	RDPRTn      = 1
	SPRMODn     = 8
	BOR_LEVn    = 16
	IWDG_SWn    = 20
	nRST_STOPn  = 21
	nRST_STDBYn = 22
	BFB2n       = 23
)
